In a synchronous computer system having a bidirectional bus, one of the signals transmitted to the bus interface circuits on each module of the system is a clock signal used to control the timing of data transfer operations. Specifically, the clock signal synchronizes the transmission and reception of data between physically separated points on the bus.
For proper operation of the computer system, clock signals should arrive at the bus interface circuitry at the same time; otherwise, reliable data transmission is not ensured. For example, if a bus interface circuit receiving data is "clocked" later than others, the earlier-clocked bus interface circuits may overwhelm the data before it is stored at its proper destination. This lack of simultaneity in reception of the clock signals, i.e., clock skew, directly increases the amount of time that the data must remain stable on the bus to ensure reliable data transmission; this, in turn, increases the time required for each data transfer on the bus and, thus reduces the speed of the bus.
The amount of clock skew introduced into a computer system is a direct function of the variations in propagation delays among clock receiver chips and velocity factor differences in module etch of the system. A chip, i.e., a small piece of silicon on which integrated circuits are formed, typically comprises transistors. In digital logic applications, a transistor switches "on", when saturated, and "off", when nonconducting, to generate full "signal" swings between two power supply voltages. The signals are in the form of "high" and "low" states of the output voltage of the transistor. Propagation delay is affected by the switching speed of the transistor and is highly dependent upon variations in the fabrication process of the chip. In addition, the applied voltage, the operating temperature and the loading conditions of the chip affect its switching speed.
For logic switching applications, the transistors of a chip are typically configured as inverter and buffer circuits. An inverter "inverts" the logic sense of a binary signal; a buffer is used merely for signal amplification. That is, the buffer circuit does not produce any particular logic function since the binary value of the output is the same as the binary value of the input. However, buffering of low-level signals with semiconductor chips to develop high-level digital pulse signals is very susceptible to propagation delay variations due to process, voltage, temperature and loading (PVTL) variations. Differences in propagation delay between clock "buffer" chips in a system directly translate into skew. Removing propagation delay, and thus delay differences, is not physically possible; however, adding delay is.
The problem of clock skew is addressed partly by employing a central system clock source and distributing the clock signals to the respective modules. Distribution is accomplished in a manner such that the clock signals arrive essentially simultaneously at the modules. In each module, the incoming clock signals are typically processed, i.e., shaped and amplified, before use by various integrated circuit (IC) chips on the module. Such processing necessarily delays the signals; the delays can be expected to vary from module to module because of PVTL variations among clock buffer chips. In addition, the clock distribution network located on each IC chip of each module can be expected to vary from chip to chip. These variations contribute significantly to clock skew and the present invention is directed to the reduction of the skew. More specifically, the present invention is directed to delivering low-skew clock signals to points on the IC chip where the clock signals are actually used, i.e., at their "points-of-use".
An example of a technique used to reduce PVTL-caused clock skew is disclosed in an article titled, CLOCK BUFFER CHIP WITH ABSOLUTE DELAY REGULATION OVER PROCESS AND ENVIRONMENTAL VARIATIONS, by Watson et al., from 1992 IEEE Custom Integrated Circuit Conference. Here, a delay regulator circuit of a clock repeater chip located on a computer module performs a precise measurement of the propagation delay of clock signal processed by the repeater chip and adjusts that delay to a standard value prior to distributing the processed clock signal to other IC chips on the module. Each repeater chip provides an interface between a globally-distributed (system) input clock signal and corresponding locally-distributed (module) output clock signals. By adjusting the delay in the chip, a fixed-phase relationship is maintained between the input and output clock signals.
Delay regulation in accordance with the above-described technique is performed with a replica loop circuit on the repeater chip that replicates the internal path delay of that chip. The delay regulator circuit described in this paper could also perform a measurement of the propagation delay of a replica of the internal clock distribution path of each IC chip that receives the processed clock signal. This would require extending the replica loop circuit onto the respective IC chip. This approach could allow the repeater chip to regulate delay originating both in itself and in these respective IC chips, in limited fashion.
However, the extended portion of the replica loop on each IC chip would require a significant number of components to accurately simulate the internal clock distribution network of that IC chip, thereby increasing the size and cost of that chip. Furthermore, each respective IC chip requires an unregulated output buffer which may be subjected to PVTL conditions different from those experienced by the repeater chip and the other IC chips, thereby introducing inaccuracies.
Therefore, it is among the objects of the present invention to provide a technique for remotely measuring, in real time, the effects of propagation delays using the actual clock distribution network of an integrated circuit chip coupled to a clock repeater chip.
Another object of the invention is to minimize the number of logic gates needed to perform remote delay regulation on the integrated circuit chip associated with the repeater chip.
Another object of the invention is to minimize the effective clock skew between points-of-use on different integrated circuit chips throughout a computer system.
Another object of the invention is to provide a technique for inserting delay into a clock distribution network with a very high degree of resolution.
Another object of the invention is to provide a technique for measuring the amount of clock delay requiring insertion from the input of the repeater chip to a point-of-use on the associated integrated circuit chip, i.e., auto ranging, despite the amount of propagation delay in the clock distribution network.
Yet another object of the invention is to minimize the lengths of clock transmission lines traversing a computer module and coupling the integrated circuit chips to the repeater chip.
Still yet another object of the invention is to minimize use of computer-aided-design tools in the design of the associated integrated circuit chip.